One technique for improving performance of a software system is to implement selected sections as hardware accelerators. Those sections of the system that exhibit high computational complexity and consume large portions of total runtime may be suitable candidates for implementing as hardware accelerators. The hardware accelerators could be application-specific integrated circuits (ASICs), graphics processing units (GPUs), or circuitry running on field programmable gate arrays (FPGAs), for example. A common approach employed by software designers in creating a hardware accelerator is to use a high-level synthesis (HLS) tool to convert the original high-level language (HLL) specification of the identified section into an equivalent register transfer level (RTL) or other hardware description language (HDL) specification of the circuit. The hardware description of the circuit can then be processed using synthesis, map, place-and-route, and bitstream generation tools to create configuration data for manufacturing a circuit or configuring programmable logic.
A typical scenario in debugging a hardware accelerator entails setting breakpoints in the HLL code and creating hardware that implements the breakpoints in the hardware accelerator. The hardware accelerator can then be run and will automatically stop when a state is reached that satisfies a specified breakpoint. Once the hardware accelerator stops, the user can read out the contents of selected registers, analyze the data, and resume running the hardware accelerator. As used herein, “stopping the clock” refers to stopping oscillations of the clock signal that drives the hardware accelerator, and “starting” or “restarting” the clock refers to enabling oscillations of the clock signal that drives the hardware accelerator.
Debugging a hardware accelerator can be extremely time-consuming. One type of breakpoint allows a user to specify a Boolean expression. In order to determine whether or not a Boolean expression has been satisfied, the clock signal that drives the hardware accelerator is stopped after each cycle to permit evaluation of the expression. If the breakpoint is satisfied, the clock remains stopped, which allows the user to examine the state of the hardware accelerator. Otherwise, the clock is automatically restarted. The repeated stopping of the clock, evaluating the expression, and restarting the clock significantly slows execution of the hardware accelerator.
Another type of breakpoint is an operation-specific breakpoint (OSBP). An OSBP involves a breakpoint set on a particular operation performed by the hardware accelerator. An OSBP can be established by setting a breakpoint on a line of HLL program code, and generating debugging circuitry that accompanies the hardware accelerator. The debugging circuitry can stop execution of the hardware accelerator when the designated operation is performed. If the operation having the breakpoint is performed repeatedly, manually restarting the clock can become tedious for the user.